Originally Aired - Tuesday, June 18 • 3:50 PM - 4:15 PM
Create or Log in to My Show Planner to see Videos and Resources.
Your account does not have access to this session.
{{chatBodyContent}}
Be sure to come back after the session starts to have access to session resources.
Location: Honolulu 3
Title: C9.2 | A 640-Gb/s 4 X 4-MIMO D-Band CMOS Transceiver Chipset
Description:
Chenxin Liu1, Zheng Li1, Yudai Yamazaki1, Hans Herdian1, Chun Wang1, Anyi Tian1, Jun Sakamaki1, Han Nie1, Xi Fu1, Sena Kato1, Wenqian Wang1, Hongye Huang1, Shinsuke Hara2, Akifumi Kasamatsu2, Hiroyuki Sakai1, Kazuaki Kunihiro1, Atsushi Shirane1, Kenichi Okada1 1Tokyo Institute of Technology, 2National Institute of Information and Communications Technology This work presents a D-band (114-170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth. An 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) are proposed to improve bandwidth and linearity. The proposed TRX chipset achieves 200-Gb/s data rate by 32QAM in the single-input single-output (SISO) over-the-air (OTA) measurement. A 120-Gb/s data rate by 16QAM is realized with a 15m distance. A 640-Gb/s 4×4 multi-input multi-output (MIMO) is also demonstrated in this work.
Authors:
Type: Circuits Technical Session
Tuesday, June 18, 2024 - 03:25 PM
C9 | Wireless Transceivers
