Originally Aired - Tuesday, June 18 • 2:20 PM - 2:45 PM
Create or Log in to My Show Planner to see Videos and Resources.
Your account does not have access to this session.
{{chatBodyContent}}
Be sure to come back after the session starts to have access to session resources.
Location: Tapa 1
Title: T2.3 | In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layer Experimental Demonstration and Modeling
Description:
Authors:
Giuk Kim1, Hyojun Choi1, Hunbeom Shin1, Sangho Lee1, Sangmok Lee1, Yunseok Nam1, Minhyun Jung1, Ilho Myeong2, Kijoon Kim2, Suhwan Lim2, Kwangsoo Kim2, Wanki Kim2, Daewon Ha2, Jinho Ahn3, Sanghun Jeon1 1KAIST, 2Samsung Electronics, 3Hanyang University
In this work, we experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)-FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized ‘positive feedback’ (Posi. FB.) of dual effects, leading to low operation voltage (VPGM/VERS: +17/-15 V), a wide memory window (MW: 10.5 V) and negligible disturb at a biased voltage of 9 V. Furthermore, our proposed model verifies that the performance enhancement of the BE-MIFIS FeFET is attributed to the intensified posi. FB. This work proves that the hafnia FE can play as a key enabler in extending the technology development of 3D VNAND, which is currently approaching a state of stagnation.
Type: Technology Technical Session
Tuesday, June 18, 2024 - 01:30 PM
T2 | Non-Volatile Memory Technology - Hafnia Based Ferroelectrics-1
