T5.1 | Product Performance Aware 3rd Generation GAA Platform Transistor Design with Extreme Small Local Layout Effect and Transistor Variation

Event Time

Wednesday, June 19 10:15 AM - 10:40 AM

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Event Location

Location: Tapa 1-3


Event Information

Title: T5.1 | Product Performance Aware 3rd Generation GAA Platform Transistor Design with Extreme Small Local Layout Effect and Transistor Variation

Description:


Authors:
Dongchan Jeong1, Seungkwon Kim1, Seulki Park1, Sang Hyeon Lee1, Sada-aki Masuoka1, Byungha Choi1, Shincheol Min1, Sanghoon Lee1, Minseong Lee1, Chang-Woo Sohn1, Jaehun Jeong1, Yuri Yasuda-Masuoka1, Ja-Hum Ku1,1 1Samsung Electronics

A product performance aware 3rd generation MBCFETTM (SF2) is revealed to maximize Gate-All-Around benefit fully by introducing unique epitaxial and integration process, which overcomes the scaling and GAA structure conflict with a product gain. The product major narrow NS Tr was boosted by N/PFET +29/+46%, as well as a wide NS Tr +11/+23%. In addition, through Tr global variation reduction by 26% from FinFET, a product leakage distribution was significantly scaled by ~50%. The process can enable another level of DTCO collaboration in MBCFETTM for the future technology

Type: Technology Technical Session


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Parent Sessions

Wednesday, June 19, 2024 - 10:15 AM
T5 | Advanced CMOS Devices and Technology-1