
Chet Lenox
Fellow
at KLA
Chet Lenox received his bachelor's degree from Texas A&M University and his MS and PhD from the University of Texas, both in Electrical Engineering. He has worked in various process development, integration, and device roles at Intel, National Semiconductor, and Texas Instruments. Chet's current role is in Industry and Customer Collaboration for KLA Corporation.
Sessions
- CW1 | High-Performance Mixed-Signal Circuit Recent Art Balancing the Analog vs. Digital
- Sunday, June 16 • 1:00 PM - 3:00 PM
- SW | Advancing SoC Design: Open-Source and ML-Driven Approaches in the Cloud
- Sunday, June 16 • 1:00 PM - 5:00 PM
- SW1: Cloud bursting an EDA workload with ML-driven technique for future SoC development
- Sunday, June 16 • 1:05 PM - 1:30 PM
- CW1-1: PLLs
- Sunday, June 16 • 1:15 PM - 1:50 PM
- SW2: Generative AI-based EDA for SoC
- Sunday, June 16 • 1:30 PM - 2:00 PM
- CW1-2: DACs
- Sunday, June 16 • 1:50 PM - 2:25 PM
- SW3: Chipyard: An Open-Source Design, Simulation, and Implementation Framework for Custom RISC-V SoCs
- Sunday, June 16 • 2:00 PM - 2:30 PM
- CW1-3: ADCs
- Sunday, June 16 • 2:25 PM - 3:00 PM
- SW4: ESP: An Open-Source Platform for Agile SoC Design
- Sunday, June 16 • 2:30 PM - 3:00 PM
- SW5: AMS generation frameworks: an industry perspective
- Sunday, June 16 • 3:10 PM - 3:35 PM
- TW2 | Novel Metals and Advanced Interconnects
- Sunday, June 16 • 3:15 PM - 6:00 PM
- TW2-1: An industry perspective of beyond Cu, alternative metal interconnects
- Sunday, June 16 • 3:30 PM - 3:55 PM
- CW2 | BioSensory Breakthrough: Pioneering the Future of Health Tech
- Sunday, June 16 • 3:30 PM - 5:30 PM
- SW6: Agile SoC Design With OpenROAD and Proprietary Flows: A Retrospective
- Sunday, June 16 • 3:35 PM - 4:00 PM
- CW2-1: Injectable Biosensors: Is there a future?
- Sunday, June 16 • 3:45 PM - 4:10 PM
- TW2-2: Replacing Tungsten and Copper by Molybdenum in logic technology
- Sunday, June 16 • 3:55 PM - 4:20 PM
- SW7: Agile-X: democratization base of innovative semiconductor technology
- Sunday, June 16 • 4:00 PM - 4:30 PM
- CW2-2: Low-Power AI-Driven Neural Interfaces for Treating Brain Disorders
- Sunday, June 16 • 4:10 PM - 4:35 PM
- TW2-3: The search for new materials for interconnects < 10 nm
- Sunday, June 16 • 4:20 PM - 4:45 PM
- SW8: Freshmen through Ph.D. students experience open-source tape-out: successes and pitfalls
- Sunday, June 16 • 4:30 PM - 5:00 PM
- CW2-3: Low-Power Bioimpedance Measurement Techniques for Sensing and Imaging
- Sunday, June 16 • 4:35 PM - 5:00 PM
- TW2-4: Opportunities and challenges of intermetallic compounds for future interconnects
- Sunday, June 16 • 4:45 PM - 5:10 PM
- CW2-4: Silicon Device based miniaturized biosensors for Healthcare & IoT
- Sunday, June 16 • 5:00 PM - 5:25 PM
- SW9: Code-a-Chip Poster Session
- Sunday, June 16 • 5:00 PM - 5:30 PM
- TW2-5: Intercalated Graphene for Advanced Interconnects
- Sunday, June 16 • 5:10 PM - 5:35 PM
- CW2-5: CMOS bioelectronics for volumetrically efficient implantables
- Sunday, June 16 • 5:25 PM - 5:50 PM
- TW2-6: Interconnect Technology/System Co-Design for VLSI Logic and Memory Systems
- Sunday, June 16 • 5:35 PM - 6:00 PM
- CW2-6: A Battery-free Sticker-like Reader for Wireless Passive Sensors
- Sunday, June 16 • 5:50 PM - 6:15 PM
- 2024 Spintronics Workshop on LSI
- Sunday, June 16 • 8:00 PM - 10:00 PM
- SC-T | Advanced VLSI technologies for next generation computing
- Monday, June 17 • 8:20 AM - 4:50 PM
- SC-C | Circuits and Systems for Heterogeneous Integration
- Monday, June 17 • 8:20 AM - 5:00 PM
- SC-C 1: Advanced Packaging Enabling Heterogeneous Integration
- Monday, June 17 • 8:30 AM - 9:20 AM
- SC-T 1: CMOS Device Scaling for Power-Performance - Key Physics and Challenges
- Monday, June 17 • 8:30 AM - 9:20 AM
- SC-T 2: Innovations of Material and Process Engineering in the Angstrom Era for Advanced CMOS Logic Technology
- Monday, June 17 • 9:20 AM - 10:10 AM
- SC-C 2: I/O design considerations for die-to-die interface
- Monday, June 17 • 9:20 AM - 10:10 AM
- SC-C 3: Directions, Challenges and Opportunities in Heterogeneous Integration
- Monday, June 17 • 10:30 AM - 11:20 AM
- SC-T 3: Integration Challenges for Pitch Scaling in Advanced BEOL Interconnects
- Monday, June 17 • 10:30 AM - 11:20 AM
- SC-T 4: Functional Backside: past, present, and STCO future
- Monday, June 17 • 11:20 AM - 12:10 PM
- SC-C 4: Heterogenous integration for automotive ICs
- Monday, June 17 • 11:20 AM - 12:10 PM
- SC-T 5: In-memory-computing with emerging memories
- Monday, June 17 • 1:10 PM - 2:00 PM
- SC-C 5: Wafer Scale System Integration Technology
- Monday, June 17 • 1:20 PM - 2:10 PM
- SC-T 6: Opportunities to break through limit and to enable prolongation of DRAM
- Monday, June 17 • 2:00 PM - 2:50 PM
- SC-C 6: Advancements in Co-Packaging and Co-Integration Technologies for High-Performance Memory Systems
- Monday, June 17 • 2:10 PM - 3:00 PM
- SC-T 7: Metrology & Inspection: Past, Present, and Future
- Monday, June 17 • 3:10 PM - 4:00 PM
- SC-C 7: Evolution and Future of Heterogenous 3D Integrated Circuits and their Design using EDA Tools
- Monday, June 17 • 3:20 PM - 4:10 PM
- SC-T 8: Silicon photonics for high bandwidth optical I/O
- Monday, June 17 • 4:00 PM - 4:50 PM
- SC-C 8: Integrated Power Delivery and Management Technologies for Heterogenous Integrated Systems
- Monday, June 17 • 4:10 PM - 5:00 PM
- Demo Sessions
- Monday, June 17 • 5:30 PM - 7:30 PM
- PL1.0 - Plenary 1 Opening & Awards
- Tuesday, June 18 • 8:00 AM - 8:20 AM
- PL1 | Opening and Plenary I
- Tuesday, June 18 • 8:00 AM - 10:00 AM
- PL1.1 | Making Sense at the Edge (Invited)
- Tuesday, June 18 • 8:35 AM - 9:15 AM
- PL1.2 | Mobility Evolution: Electrification and Automation (Invited)
- Tuesday, June 18 • 9:15 AM - 10:00 AM
- C1.1 | A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect
- Tuesday, June 18 • 10:15 AM - 10:40 AM
- C2.1 | A Monolithic Low-ILEAK Cross-Coupled GaN Driver with &[Delta]&[Phi]-Reduced EMI-Rejecter for 21.51dBµV-EMI-Reduction and 1/10x filter-capacitor
- Tuesday, June 18 • 10:15 AM - 10:40 AM
- C3.1 | 122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm
- Tuesday, June 18 • 10:15 AM - 10:40 AM
- T1.1 | An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications
- Tuesday, June 18 • 10:15 AM - 10:40 AM
- C2 | Power at High Voltage and Current
- Tuesday, June 18 • 10:15 AM - 12:20 PM
- C3 | AI/ML Accelerators and CiM
- Tuesday, June 18 • 10:15 AM - 12:20 PM
- C1 | Wireline Circuits
- Tuesday, June 18 • 10:15 AM - 12:20 PM
- T1 | Technology Highlights
- Tuesday, June 18 • 10:15 AM - 12:20 PM
- T1.2 | Highly manufacturable Self-Aligned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch
- Tuesday, June 18 • 10:40 AM - 11:05 AM
- C1.2 | A 2 × 56 Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS
- Tuesday, June 18 • 10:40 AM - 11:05 AM
- C2.2 | A Monolithic GaN-based Gate Driver for LLC-SRC with Three-Phase Startup Clamping Achieving 23.2µA IQ and 98.6% Peak Efficiency
- Tuesday, June 18 • 10:40 AM - 11:05 AM
- C3.2 | FSNAP: An Ultra-Energy-Efficient Few-Spikes-Neuron based Reconfigurable SNN Processor Enabling Unified On-Chip Learning and Accuracy-Driven Adaptive Time-Window Tuning
- Tuesday, June 18 • 10:40 AM - 11:05 AM
- C3.3 | ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction
- Tuesday, June 18 • 11:05 AM - 11:30 AM
- C2.3 | A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density
- Tuesday, June 18 • 11:05 AM - 11:30 AM
- C1.3 | A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2
- Tuesday, June 18 • 11:05 AM - 11:30 AM
- T1.3 | A confined storage nitride 3D-NAND cell with WL airgap for cell-to-cell interference reduction and improved program performances
- Tuesday, June 18 • 11:05 AM - 11:30 AM
- T1.4 | On the extreme scaling of transistors with monolayer MoS2 channel
- Tuesday, June 18 • 11:30 AM - 11:55 AM
- C1.4 | A 200-Gb/s PAM-4 transmitter with 1.6-Vppd output swing and clock skew correction in 12-nm FinFET
- Tuesday, June 18 • 11:30 AM - 11:55 AM
- C2.4 | A ±100A Auto-Calibration Current Sensor with 80V Pulse-Width Modulation Attenuation and 0.15% Gain Error
- Tuesday, June 18 • 11:30 AM - 11:55 AM
- C3.4 | A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation
- Tuesday, June 18 • 11:30 AM - 11:55 AM
- C3.5 | A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera
- Tuesday, June 18 • 11:55 AM - 12:20 PM
- C2.5 | A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6% High Efficiency and Fast Transient Response
- Tuesday, June 18 • 11:55 AM - 12:20 PM
- C1.5 | A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1Vppd Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS
- Tuesday, June 18 • 11:55 AM - 12:20 PM
- T1.5 | First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory
- Tuesday, June 18 • 11:55 AM - 12:20 PM
- Women in Circuits/Electron Devices Lunch
- Tuesday, June 18 • 12:00 PM - 1:15 PM
- C4.1 | A Wireless Neurostimulator using Body-Coupled Link for Multisite Stimulation in Freely Behaving Animals
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- C5.1 | A 15.4ppm/ºC GaN-based Voltage Reference with Process-Variation-Immunity and High PSR for EV Power Systems
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- C6.1 | 3D-Stacked 1Megapixel Time-Gated SPAD Image Sensor with 2D Interactive Gating Network for Image Alignment-Free Sensor Fusion
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- JFS1.1 | First Radio-Frequency Circuits fabricated in top-tier of a full 3D Sequential Integration Process at mmW for 5G applications
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- JFS2.1 | CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- T2.1 | HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85° C
- Tuesday, June 18 • 1:30 PM - 1:55 PM
- C4 | Biomedical Stimulation and Imaging
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- C5 | Analog Techniques
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- C6 | SPAD Sensors
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- JFS1 | RF, mmWave, and THz Technologies
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- JFS2 | Processors & Compute
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- T2 | Non-Volatile Memory Technology - Hafnia Based Ferroelectrics-1
- Tuesday, June 18 • 1:30 PM - 3:10 PM
- JFS1.2 | A 140-Gbps 1-to-21GHz Ultra-Wideband LNA Achieving 1.95-to-3dB NF Using Gm-Assisted-Feedback Noise Suppression Technique in 40nm Bulk CMOS
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- JFS2.2 | NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- C6.2 | A 512x512 SPAD Laser Speckle Autocorrelation Imager in Stacked 65/40nm CMOS
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- C5.2 | A 97.3dB SNR Bioimpedance AFE with -84dB THD Segmented-ΔΣM Sinusoidal Current Generator and Passing-Through Instrumentation Amplifier
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- C4.2 | A Current-Source-Free Constant-Current Wireless Adiabatic Neural Stimulator Achieving a 5.5-27.7x Improved RF-to-Electrode Stimulation Efficiency Factor
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- T2.2 | Polar axis orientation control of hafnium-based ferroelectric capacitors with in-situ AC electric bias during rapid thermal annealing
- Tuesday, June 18 • 1:55 PM - 2:20 PM
- T2.3 | In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layer Experimental Demonstration and Modeling
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- C4.3 | A 5.7kfps Fast Neural Electrical Impedance Tomography IC Based on Incremental Zoom Structure with Baseline Cancellation for Peripheral Nerve Monitoring Systems
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- C5.3 | A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output Common-Mode Compensation Technique for Wide Output Power Range
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- C6.3 | A Digital Dynamic Vision Sensor with SPAD pixels and Multi-Event Generation for Motion/Vibration-Adaptive Detection
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- JFS1.3 | First Heterogeneous and Monolithic 3D (HM3D) Integration of InGaAs HEMTs and InP/InGaAs DHBTs on Si CMOS for Next-Generation Wireless Communication
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- JFS2.3 | A Quad-Core AI Processing Unit for Generative AI in 4nm 5G Smartphone SoC (Invited)
- Tuesday, June 18 • 2:20 PM - 2:45 PM
- JFS2.4 | AMD InstinctTM MI300X Accelerator: Packaging and Architecture Co-Optimization (Invited)
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- JFS1.4 | Terahertz Sensing with CMOS-RFIC - Feasibility Verification for Short-Range Imaging using 300GHz MIMO Radar (Invited)
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- C6.4 | A 7.2inch 5.5Mpixel 600mW SPAD X-ray Detector with 116.7 dB Dynamic Range
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- C5.4 | Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- C4.4 | A Fully Dynamic 1st-Order 1st-Order Δ-ΔΣ Modulator with a 468mVInput Range for Electrical Impedance Tomography Systems
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- T2.4 | Unveiling Cryogenic Performance (4 to 300 K) towards Ultra-thin Ferroelectric HZO: Novel Kinetic Barrier Engineering and Underlying Mechanism
- Tuesday, June 18 • 2:45 PM - 3:10 PM
- C7.1 | Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- C8.1 | A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCOΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- C9.1 | A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- JFS3.1 | Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators (Invited)
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- T4.1 | Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- T3.1 | Record Performance in GAA 2D NMOS and PMOS using Monolayer MoS2 and WSe2 with scaled contact and gate length
- Tuesday, June 18 • 3:25 PM - 3:50 PM
- C7 | Processors I
- Tuesday, June 18 • 3:25 PM - 5:05 PM
- C8 | Oversampled Converters
- Tuesday, June 18 • 3:25 PM - 5:30 PM
- C9 | Wireless Transceivers
- Tuesday, June 18 • 3:25 PM - 5:30 PM
- JFS3 | Thermal Management and Power Delivery in 3D Integration
- Tuesday, June 18 • 3:25 PM - 5:30 PM
- T3 | Novel Channel Materials for Advanced CMOS
- Tuesday, June 18 • 3:25 PM - 5:30 PM
- T4 | Oxide Channel FET for Logic and Memory Applications-1
- Tuesday, June 18 • 3:25 PM - 5:30 PM
- T3.2 | EOT scaling via 300mm MX2 dry transfer - Steps toward a manufacturable process development and device integration.
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- T4.2 | Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration - ALD Material Engineering, High-Field Transport, Statistical Variability
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- JFS3.2 | 3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects (Invited)
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- C9.2 | A 640-Gb/s 4 X 4-MIMO D-Band CMOS Transceiver Chipset
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- C8.2 | A 470μW, 102.6dB-DR, 20kHz BW calibration-free ΔΣ Modulator with SFDR in excess of 110dBc using an Intrinsically Linear 13-Level DAC
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- C7.2 | A 52.01TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication
- Tuesday, June 18 • 3:50 PM - 4:15 PM
- C7.3 | A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6. .6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- C8.3 | A Beyond-the-rail Audio CTDSM with a Passive Input Stage and 99.2dB SNDR
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- C9.3 | A -96.5 dBm-Sensitivity, 14 dBm peak power, Self-Interference Resistant IR-UWB Radar Transceiver Supporting Child Presence Detection and Precision Positioning
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- JFS3.3 | Package - System Thermal Modeling and New Material (Invited)
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- T4.3 | Enhancement of In2O3 Field-Effect Mobility Up To 152 cm2·V-1·s-1 Using HZO-Based Higher-k Linear Dielectric
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- T3.3 | High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure
- Tuesday, June 18 • 4:15 PM - 4:40 PM
- T3.4 | Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors with CMOS-Friendly Approaches
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- T4.4 | Highly Enhanced Memory Window of 17.8V in Ferroelectric FET with IGZO Channel via Introduction of Intermediate Oxygen-deficient Channel and Gate Interlayer
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- JFS3.4 | Integration and Characterization of High Thermal Conductivity Materials for Heat Dissipation in Stacked Devices
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- C9.4 | A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- C8.4 | A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-order Continuous-Time Delta-Sigma Modulator with 3rd-order Noise Coupling
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- C7.4 | Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
- Tuesday, June 18 • 4:40 PM - 5:05 PM
- C8.5 | A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers
- Tuesday, June 18 • 5:05 PM - 5:30 PM
- C9.5 | A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond (Late News)
- Tuesday, June 18 • 5:05 PM - 5:30 PM
- JFS3.5 | High thermal conductivity AlN films for advanced 3D Chiplets
- Tuesday, June 18 • 5:05 PM - 5:30 PM
- T4.5 | a-IGZO FETs with High Current and Remarkable Stability for Vertical Channel Transistor(VCT) DRAM Applications
- Tuesday, June 18 • 5:05 PM - 5:30 PM
- T3.5 | Single-crystalline monolayer MoS2 arrays based high-performance transistors via selective-area CVD growth directly on silicon wafers
- Tuesday, June 18 • 5:05 PM - 5:30 PM
- IEEE Young Professionals Micro-Mentoring and Networking Session
- Tuesday, June 18 • 5:30 PM - 7:30 PM
- EP | Evening Panel: Will AI Bite the Industry That Feeds It?
- Tuesday, June 18 • 8:00 PM - 10:00 PM
- PL2.0 - Plenary 2 Awards
- Wednesday, June 19 • 8:00 AM - 8:20 AM
- PL2 | Plenary Session II
- Wednesday, June 19 • 8:00 AM - 10:00 AM
- PL2.1 | Wireless and Future Hyperconnected World (Invited)
- Wednesday, June 19 • 8:35 AM - 9:15 AM
- PL2.2 | Photonics-Electronics Convergence Devices to Accelerate IOWN (Invited)
- Wednesday, June 19 • 9:15 AM - 10:00 AM
- C10.1 | MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating
- Wednesday, June 19 • 10:15 AM - 10:40 AM
- C11.1 | A 0.9V Rail-to-Rail Ultra-Low-Power Fully Integrated Clock Generator Achieving 23fJ/Cycle in 28nm CMOS
- Wednesday, June 19 • 10:15 AM - 10:40 AM
- C12.1 | 23,000-Exposures/s 360fps-Readout Software-Defined Image Sensor with Motion-Adaptive Spatially Varying Imaging Speed
- Wednesday, June 19 • 10:15 AM - 10:40 AM
- T5.1 | Product Performance Aware 3rd Generation GAA Platform Transistor Design with Extreme Small Local Layout Effect and Transistor Variation
- Wednesday, June 19 • 10:15 AM - 10:40 AM
- T5 | Advanced CMOS Devices and Technology-1
- Wednesday, June 19 • 10:15 AM - 11:55 AM
- C10 | Transformer Processors
- Wednesday, June 19 • 10:15 AM - 11:55 AM
- C11 | Clocking Techniques
- Wednesday, June 19 • 10:15 AM - 11:55 AM
- C12 | Sensors for Audio and Video
- Wednesday, June 19 • 10:15 AM - 11:55 AM
- C12.2 | A 450μW@50fps Wake-Up Module Featuring Auto-Bracketed 3-Scale Log-Corrected Pattern Recognition and Motion Detection in a 1.5Mpix 8T Global Shutter Imager
- Wednesday, June 19 • 10:40 AM - 11:05 AM
- C11.2 | A 94fsrms-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch
- Wednesday, June 19 • 10:40 AM - 11:05 AM
- C10.2 | A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-assisted Cores
- Wednesday, June 19 • 10:40 AM - 11:05 AM
- T5.2 | Monolithic Complementary Field Effect Transistors (CFET) demonstrated using Middle Dielectric Isolation and Stacked Contacts
- Wednesday, June 19 • 10:40 AM - 11:05 AM
- T5.3 | Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-high Hole Mobility
- Wednesday, June 19 • 11:05 AM - 11:30 AM
- C10.3 | A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-based Speculation
- Wednesday, June 19 • 11:05 AM - 11:30 AM
- C11.3 | A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling
- Wednesday, June 19 • 11:05 AM - 11:30 AM
- C12.3 | A 430-μA 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone based on Electrostatic Force Feedback Control
- Wednesday, June 19 • 11:05 AM - 11:30 AM
- C12.4 | A 1.5 V 132 dBSPL AOP Digital Readout Circuit for MEMS Microphone Using Self-Adaption Loop
- Wednesday, June 19 • 11:30 AM - 11:55 AM
- C11.4 | A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems
- Wednesday, June 19 • 11:30 AM - 11:55 AM
- C10.4 | A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating
- Wednesday, June 19 • 11:30 AM - 11:55 AM
- T5.4 | Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5)
- Wednesday, June 19 • 11:30 AM - 11:55 AM
- T6.1 | Fluorine-free Word Line Molybdenum Process for Enhancing Scalability and Reliability in 3D Flash Memory
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- C13.1 | Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-based In-Memory Encryption Macro for Dynamic Edge Security
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- C15.1 | A 76 X 55 X-Ray Energy Binning Dosimeter for Closed-Loop Cancer Radiotherapy,
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- C14.1 | A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9µm-pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- TFS1.1 | Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits (Invited)
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- TFS2.1 | Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect Innovation (Invited)
- Wednesday, June 19 • 1:00 PM - 1:25 PM
- TFS1 | Oxide Semiconductor Applications in BEOL
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- TFS2 | Backside of Silicon: From Power Delivery to Signaling
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- C13 | Security
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- C14 | Very High-Speed Wireline
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- C15 | Interfaces to the Human Body and Sequencing
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- T6 | Memory Technology: NAND, DRAM-1
- Wednesday, June 19 • 1:00 PM - 3:05 PM
- C13.2 | A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- C14.2 | A 1.1pJ/b/lane, 1.8Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation using TX-FFE in 5nm CMOS
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- C15.2 | A 2000-Volumes/s 3D Ultrasound Imaging Chip with Monolithically-Integrated 11.7x23.4mm2 2048-Element CMUT Array and Arbitrary-Wave TX Beamformer
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- T6.2 | Innovative Barrier Metal-less Metal Gate Scheme leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- TFS2.2 | A Design Methodology for Back-side Power and Clock Routing Co-Optimization (Invited)
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- TFS1.2 | P-type SnO Semiconductor Transistor and Application (Invited)
- Wednesday, June 19 • 1:25 PM - 1:50 PM
- TFS1.3 | Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide Power Transistors and Superlattice MIM Capacitors
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- TFS2.3 | Backside power distribution for nanosheet technologies beyond 2nm
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- T6.3 | Mechanical Stress Effects on Dielectric Leakage and Interconnection Integrity in 3D NAND Flash Memory
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- C15.3 | A Smart Contact Lens System with 433MHz Wireless Power and Data Transfer at a Modulation Index Down to 0.02%
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- C14.3 | A 0.9pj/b 9.8-113Gb/s XSR Serdes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- C13.3 | A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competition in 28nm CMOS with 5e-9 Bit Error Rate
- Wednesday, June 19 • 1:50 PM - 2:15 PM
- C13.4 | An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for Trustworthy Sensing
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- C14.4 | A 4x50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- C15.4 | An Intra-Body-Power-Transfer System Energized by an Electromagnetic Energy Harvester for Powering Wearable Sensor Nodes
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- T6.4 | Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-size Control, Material Selection, and Seam Removal
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- TFS2.4 | Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications beyond 2nm Node
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- TFS1.4 | First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory
- Wednesday, June 19 • 2:15 PM - 2:40 PM
- TFS1.5 | On the Reliability of High-Performance Dual Gate (DG) W-doped In2O3 FET
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- TFS2.5 | Backside Power Delivery in High Density and High Performance Context: IR-drop and Block-level Power-Performance-Area Benefits
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- T6.5 | A Metal Dual Work-function Gate (MDWG) for the continuous scaling of DRAM Cell Transistors
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- C15.5 | A 28nm Approximate / Binary 6T CAM for Sequence Alignment
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- C14.5 | A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection applications in 5nm FinFet Process
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- C13.5 | A 65nm Delta-Sigma ADC based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability down to 0.25&[Omega]
- Wednesday, June 19 • 2:40 PM - 3:05 PM
- C17.1 | A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- C16.1 | An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- C18.1 | A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- T7.1 | A New Industry Standard Compact Model Integrating TCAD into SPICE
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- T8.1 | Highly Scalable Vertical Bypass RRAM (VB-RRAM) for 3D V-NAND Memory
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- T9.1 | Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture
- Wednesday, June 19 • 3:20 PM - 3:45 PM
- T7 | Reliability, Characterization & Modeling of Oxide Semiconductor and Si Devices-1
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- T8 | Emerging Non-Volatile Memories - RRAM, FeRAM, PCM, MRAM-1
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- T9 | Monolithic and Heterogeneous Integration
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- C16 | Memory Circuits
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- C17 | Power Management Techniques
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- C18 | Data Converter Techniques
- Wednesday, June 19 • 3:20 PM - 5:25 PM
- C18.2 | A Low-OSR 5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust Differential V-T-V Converter
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- C16.2 | A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- C17.2 | A µW Output Power, >100V, Single-Capacitor Switched DC-DC Up/Down Converter
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- T7.2 | Hot-Carrier-Degradation Characterization for Accurate End-of-Life Prediction with 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FET
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- T9.2 | Mitigating line-break defectivity with a sandwiched TiN or W layer for metal pitch 18 nm aspect ratio 6 semi-damascene interconnects
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- T8.2 | A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ∆Ion 2µA/cell for 3D Stackable 4F2 High Speed Memory
- Wednesday, June 19 • 3:45 PM - 4:10 PM
- T8.3 | A Novel Chalcogenide Based CuGeSe Selector Only Memory (SOM) for 3D Xpoint and 3D Vertical Memory Applications
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- T9.3 | Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- T7.3 | Assessment of the transient self-heating effect and its impact on the performance of Watt-level RF power amplifier in a FinFET technology
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- C17.3 | A 6.78 MHz Wireless Power and Data Transfer System Achieving Simultaneous 52.6% End-to-End Efficiency and 4.0 Mb/s Forward Data Delivery with Interference-Free Rectifier
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- C16.3 | A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- C18.3 | Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder With 0.012mm2 Active Area in 12nm FinFET
- Wednesday, June 19 • 4:10 PM - 4:35 PM
- C18.4 | A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip Bit-Weight Calibration
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- C16.4 | A 3.3GHz 1048X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- C17.4 | A 0.6-1 V VIN Soft-Switching Low Dropout Regulator With 31.3 A/mm2 Current Density, 99.99% Current Efficiency, and 2.04 fs FoM
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- T7.4 | Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- T9.4 | Toward 0 V ESD protection in 2.5D/3D advanced bonding technology
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- T8.4 | First Demonstration of BEOL-Compatible Vertical Fe-NOR
- Wednesday, June 19 • 4:35 PM - 5:00 PM
- T8.5 | Reliable Low-voltage FeRAM Capacitors for High-speed Dense Embedded Memory in Advanced CMOS
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- T9.5 | Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in conjunction with Backside Power Delivery
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- T7.5 | First Observation of Time Exponent Variations under Positive Bias Stress on a-IGZO Transistors Utilizing Ultrafast On-the-Fly Technique with 1 &[micro]s Delay
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- C17.5 | A 400-ns-Settling-Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- C16.5 | A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- C18.5 | A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS
- Wednesday, June 19 • 5:00 PM - 5:25 PM
- Banquet
- Wednesday, June 19 • 7:00 PM - 9:00 PM
- C19.1 | An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology
- Thursday, June 20 • 8:00 AM - 8:25 AM
- C20.1 | Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow
- Thursday, June 20 • 8:00 AM - 8:25 AM
- T10.1 | A Novel Phase Change Material RF Switch with 16nm Technology to Achieve Low Voltage and Low Ron*Coff for mmWave
- Thursday, June 20 • 8:00 AM - 8:25 AM
- JFS4.1 | Highly Sensitive Multimodal CMOS Antifouling Sensor Array with Multi-Use Electrodes for Single-Cell-Level Profiling of Biophysical and Biochemical Parameters
- Thursday, June 20 • 8:00 AM - 8:25 AM
- JFS5.1 | A 336 x 240 backside-illuminated 3D-stacked 7µm SPAD for LiDAR sensor with PDE 28% at 940nm and under 0.4% depth accuracy up to 10m
- Thursday, June 20 • 8:00 AM - 8:25 AM
- C21.1 | A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9mV Ripple and 2.1mV Mode-Change Fluctuation for Mobile OLED Displays
- Thursday, June 20 • 8:00 AM - 8:25 AM
- C20 | Processing for AI
- Thursday, June 20 • 8:00 AM - 9:40 AM
- C21 | Power Converters
- Thursday, June 20 • 8:00 AM - 9:40 AM
- C19 | 2.5/3D Die-to-Die Interfaces
- Thursday, June 20 • 8:00 AM - 9:40 AM
- T10 | Emerging Non-Volatile Memories - RRAM, FeRAM, PCM, MRAM-2
- Thursday, June 20 • 8:00 AM - 9:40 AM
- JFS4 | Biomedical Technologies
- Thursday, June 20 • 8:00 AM - 9:40 AM
- JFS5 | Image Sensors
- Thursday, June 20 • 8:00 AM - 9:40 AM
- JFS5.2 | A Temporal Noise Reduction via 40% Enhanced Conversion Gain in Dual-Pixel CMOS Image Sensor with Full-Depth Deep-Trench Isolation and Locally Lowered-Stack Technology
- Thursday, June 20 • 8:25 AM - 8:50 AM
- C20.2 | A PVT Robust Signed 8-Bit Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications
- Thursday, June 20 • 8:25 AM - 8:50 AM
- C19.2 | Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology
- Thursday, June 20 • 8:25 AM - 8:50 AM
- C21.2 | A 1.8V-Input 0.2-to-1.5V-Output 2.5A 930mA/mm3 Always-Balanced Dual-Path Hybrid Buck Converter with Seamlessly All-VCR-Coverable Tri-Mode Operation
- Thursday, June 20 • 8:25 AM - 8:50 AM
- JFS4.2 | A 65nm Neuromorphic Bio-signal Encoder with Compute-in-Entropy Architecture 7.13nJ Privacy-preserving Encoding and 2.38Mb/mm2 Encoding Memory Density
- Thursday, June 20 • 8:25 AM - 8:50 AM
- T10.2 | 14nm FinFET node embedded MRAM technology for automotive non-volatile RAM applications with endurance over 1E12-cycles
- Thursday, June 20 • 8:25 AM - 8:50 AM
- T10.3 | Extremely scaled perpendicular SOT-MRAM array integration on 300mm wafer
- Thursday, June 20 • 8:50 AM - 9:15 AM
- JFS4.3 | A Subcellular-Resolution Multimodal CMOS Biosensor Array with 16K Ion-Selective Pixels for Real-Time Monitoring Potassium Dynamics
- Thursday, June 20 • 8:50 AM - 9:15 AM
- JFS5.3 | High-Resolution and Compact Integrated FMCW-LiDAR Chip with 128 Channels of Slow Light Grating Antennas
- Thursday, June 20 • 8:50 AM - 9:15 AM
- C21.3 | A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control
- Thursday, June 20 • 8:50 AM - 9:15 AM
- C19.3 | A 32Gb/s 0.36pJ/bit 3nm Chiplet IO using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring
- Thursday, June 20 • 8:50 AM - 9:15 AM
- C20.3 | A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro
- Thursday, June 20 • 8:50 AM - 9:15 AM
- C20.4 | A Delta-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11µW/Ch
- Thursday, June 20 • 9:15 AM - 9:40 AM
- C21.4 | 730-790mA/mm2 48V-to-1V Integrated Hybrid DC-DC Converters based on a Star-Delta Switching Network with 5x/8x Duty Expansion
- Thursday, June 20 • 9:15 AM - 9:40 AM
- JFS5.4 | A 30fps 64 X 64 CMOS Flash LiDAR Sensor with Push-Pull Analog Counter Achieving 0.1% Depth Uncertainty at 70m Detection Range
- Thursday, June 20 • 9:15 AM - 9:40 AM
- JFS4.4 | A Pulsed Electrochemistry Readout IC with Slew-rate Booting Technique and Phase-domain ∆Σ ADC for Si-Nanowire Electrical Double-layer Capacitance Measurement
- Thursday, June 20 • 9:15 AM - 9:40 AM
- T10.4 | First demonstration of high retention energy barriers and 2 ns switching, using magnetic ordered-alloy-based STT MRAM devices
- Thursday, June 20 • 9:15 AM - 9:40 AM
- T11.1 | Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs using Rare-Earth Oxide-based Dipole-First Gate Stack Compatible with CFET Integration
- Thursday, June 20 • 9:55 AM - 10:20 AM
- JFS6.1 | State-Independent Low Resistance Drift SiSbTe Phase Change Memory for Analog In-Memory Computing Applications (Invited)
- Thursday, June 20 • 9:55 AM - 10:20 AM
- T12.1 | Overcoming Performance Limitation of IGZO FET by iCVD Fluorine Doping
- Thursday, June 20 • 9:55 AM - 10:20 AM
- C22.1 | A 256Gbps Microring-based WDM Transceiver with Error-free Wide Temperature Operation for Co-packaged Optical I/O Chiplets
- Thursday, June 20 • 9:55 AM - 10:20 AM
- C24.1 | A 12-bit 16GS/s Single-channel RF-DAC with Hybrid Segmentation for Digital Back-off and Code-dependent Free Switch Driver achieving -85dBc IMD3 in 5nm FinFET
- Thursday, June 20 • 9:55 AM - 10:20 AM
- C23.1 | SPIRIT: A Seizure Prediction SoC with a 17.2nJ/cls Unsupervised Online-Learning Classifier and Zoom Analog Frontends
- Thursday, June 20 • 9:55 AM - 10:20 AM
- C22 | Wireline Circuits II
- Thursday, June 20 • 9:55 AM - 12:00 PM
- C23 | Neural Recording Interfaces
- Thursday, June 20 • 9:55 AM - 12:00 PM
- C24 | High-Speed Data Converters
- Thursday, June 20 • 9:55 AM - 12:00 PM
- JFS6 | Memory-Centric Computing for LLM
- Thursday, June 20 • 9:55 AM - 12:00 PM
- T11 | Advanced CMOS Devices and Technology-2
- Thursday, June 20 • 9:55 AM - 12:00 PM
- T12 | Oxide Channel FET for Logic and Memory Applications-2
- Thursday, June 20 • 9:55 AM - 12:00 PM
- T12.2 | Ge-doped In2O3: First Demonstration of Utlizing Ge as Oxygen Vacancy Consumer to Break the Mobility/Reliability Tradeoff for High Performance Oxide TFTs
- Thursday, June 20 • 10:20 AM - 10:45 AM
- C23.2 | A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording
- Thursday, June 20 • 10:20 AM - 10:45 AM
- C24.2 | A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS
- Thursday, June 20 • 10:20 AM - 10:45 AM
- C22.2 | A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS
- Thursday, June 20 • 10:20 AM - 10:45 AM
- JFS6.2 | Cost-effective LLM accelerator using processing in memory technology (Invited)
- Thursday, June 20 • 10:20 AM - 10:45 AM
- T11.2 | Replacement Metal Gate Process Extendible Beyond 2 nm Node with Superior Gate Conductivity
- Thursday, June 20 • 10:20 AM - 10:45 AM
- T11.3 | Breakthrough processes for Si CMOS devices with BEOL compatibility for 3D sequential integrated More than Moore analog applications
- Thursday, June 20 • 10:45 AM - 11:10 AM
- JFS6.3 | An Ultra-low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator
- Thursday, June 20 • 10:45 AM - 11:10 AM
- T12.3 | First Demonstration of Monolithic Three-dimensional Integration of Ultra-high Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-low Latency (<10ns), Record-low Energy (<10fJ) of Data Transfer and Ultra-long data retention (>5000s)
- Thursday, June 20 • 10:45 AM - 11:10 AM
- C22.3 | A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces
- Thursday, June 20 • 10:45 AM - 11:10 AM
- C24.3 | A 5nm 60GS/s 7b 64-way Time Interleaved Partial loop unrolled SAR ADC achieving 34dB SNDR up to 32GHz
- Thursday, June 20 • 10:45 AM - 11:10 AM
- C23.3 | A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking
- Thursday, June 20 • 10:45 AM - 11:10 AM
- C23.4 | A 3072-Channel Neural Readout IC with Multiplexed Two-Step Incremental-SAR Conversion and Bulk-DAC-Based EDO Compensation in 22nm FDSOI
- Thursday, June 20 • 11:10 AM - 11:35 AM
- C24.4 | A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET
- Thursday, June 20 • 11:10 AM - 11:35 AM
- C22.4 | A 2 X 112 Gb/s 0.34 pJ/b/lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS
- Thursday, June 20 • 11:10 AM - 11:35 AM
- JFS6.4 | A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications
- Thursday, June 20 • 11:10 AM - 11:35 AM
- T11.4 | First Experimental Demonstration of Self-aligned Flip FET (FFET): a Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-side Active and Interconnects
- Thursday, June 20 • 11:10 AM - 11:35 AM
- T12.4 | A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications
- Thursday, June 20 • 11:10 AM - 11:35 AM
- T12.5 | Bit-cost-scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-around and Channel-around IGZO FETs
- Thursday, June 20 • 11:35 AM - 12:00 PM
- T11.5 | 3DIC with Stacked FinFET, Inter-level Metal, and Field-Size (25x33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi
- Thursday, June 20 • 11:35 AM - 12:00 PM
- JFS6.5 | Monolithic 3D Integration of Analog RRAM-based Fully Weight Stationary and Novel CFET 2T0C-based Partially Weight Stationary for Accelerating Transformer
- Thursday, June 20 • 11:35 AM - 12:00 PM
- C22.5 | A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology
- Thursday, June 20 • 11:35 AM - 12:00 PM
- C24.5 | A 10GS/s Hierarchical Time-Interleaved ADC for RF-sampling applications
- Thursday, June 20 • 11:35 AM - 12:00 PM
- C23.5 | A 16-Ch CMI-Tolerant Neural AFE with Inherent CM Detection and Shared CM Suppression Achieving 0.006mm2/Ch and 3.1micronW/Ch
- Thursday, June 20 • 11:35 AM - 12:00 PM
- Thursday Luncheon Presentation
- Thursday, June 20 • 12:15 PM - 1:15 PM
- C26.1 | A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates
- Thursday, June 20 • 1:30 PM - 1:55 PM
- C27.1 | An OLED Display Driver IC Embedding -63dB CMR, 80mV/nA Sensitivity, 390pA Detectable, and Column-Parallel Pixel Current Readout for Real-Time Non-Uniformity Compensation
- Thursday, June 20 • 1:30 PM - 1:55 PM
- C25.1 | A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy
- Thursday, June 20 • 1:30 PM - 1:55 PM
- T13.1 | 71 GHz-fmax β-Ga2O3-on-SiC RF power MOSFETs with record Pout=3.1 W/mm and PAE=50.8% at 2 GHz, Pout= 2.3 W/mm at 4 GHz, and low microwave noise figure
- Thursday, June 20 • 1:30 PM - 1:55 PM
- T14.1 | Concatenated Continuous Driving for Extending Lifetime of Spin Qubits towards a Scalable Silicon Quantum Computer
- Thursday, June 20 • 1:30 PM - 1:55 PM
- T13 | Technologies for Power & RF Applications
- Thursday, June 20 • 1:30 PM - 3:10 PM
- T14 | Novel Devices for Quantum Computing Applications
- Thursday, June 20 • 1:30 PM - 3:10 PM
- C25 | Digital Circuits
- Thursday, June 20 • 1:30 PM - 3:10 PM
- C26 | Analog Techniques II
- Thursday, June 20 • 1:30 PM - 3:10 PM
- C27 | Sensors and Displays
- Thursday, June 20 • 1:30 PM - 3:10 PM
- T14.2 | Single-power-supply compatible cryogenic In0.8Ga0.2As quantum-well HEMTs with record combination of high-frequency and low-noise performance for quantum-computing applications
- Thursday, June 20 • 1:55 PM - 2:20 PM
- T13.2 | Field Plate and Package Optimization for GaN Devices and Systems
- Thursday, June 20 • 1:55 PM - 2:20 PM
- C25.2 | An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process
- Thursday, June 20 • 1:55 PM - 2:20 PM
- C27.2 | A 92.8% Power Reduction Event-Driven Dual-Mode Touch Analog Front-End IC Featuring 620&[mu]W Self-Capacitance Sensing and 500fps Mutual-Capacitance Sensing
- Thursday, June 20 • 1:55 PM - 2:20 PM
- C26.2 | A 0.8V Capacitively-Biased BJT-Based Temperature Sensor with an Inaccuracy of ± 0.4°C (3σ) from -40°C to 125°C in 22nm CMOS
- Thursday, June 20 • 1:55 PM - 2:20 PM
-
C26.3 | A 0.29pJ/step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensing in Spinal Implants Using RC Bridge
- Thursday, June 20 • 2:20 PM - 2:45 PM
- C27.3 | A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
- Thursday, June 20 • 2:20 PM - 2:45 PM
- C25.3 | A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics
- Thursday, June 20 • 2:20 PM - 2:45 PM
- T13.3 | Hybrid Integration of 3D-RF Interconnects on AlGaN/GaN/Si HEMT RF Transistor featuring 2.2W/mm Psat & 41% PAE @28GHz using a Robust and Cost-Effective Chiplet Heterogeneous Bonding Technique
- Thursday, June 20 • 2:20 PM - 2:45 PM
- T14.3 | First Demonstration of Superconducting Nb Contact on Heavily-Doped Group IV Semiconductor
- Thursday, June 20 • 2:20 PM - 2:45 PM
- T14.4 | Photon-mediated charge transport and stability of physically-defined and self-organized germanium quantum dots/SON barriers in few-hole regime at T > 10 K
- Thursday, June 20 • 2:45 PM - 3:10 PM
- T13.4 | Novel Material, Process and Device Innovations for Next Generation Silicon Carbide (SiC) Trench MOSFET Technology
- Thursday, June 20 • 2:45 PM - 3:10 PM
- C25.4 | A Jammer-Mitigating 267Mb/s 3.78mm2 583mW 32x8 Multi-User MIMO Receiver in 22FDX
- Thursday, June 20 • 2:45 PM - 3:10 PM
- C27.4 | E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual- Function Harvesting from Breathing, and No High-Voltage CMOS Process
- Thursday, June 20 • 2:45 PM - 3:10 PM
- C26.4 | A 0.72nW, 0.006mm2 32kHz Crystal Oscillator with Adaptive Sub-Harmonic Pulse Injection from -40°C to 125°C in 22nm FDSOI
- Thursday, June 20 • 2:45 PM - 3:10 PM
- C28.1 | Medus A 0.83/4.6 µJ/Frame 86/91.6%-CIFAR-10 tinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS
- Thursday, June 20 • 3:25 PM - 3:50 PM
- C29.1 | A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-band Noise Improvement
- Thursday, June 20 • 3:25 PM - 3:50 PM
- T15.1 | Low-Damage Processed and High-Pressure Annealed High-κ Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-κ of 70 for DRAM Technology
- Thursday, June 20 • 3:25 PM - 3:50 PM
- T17.1 | DRAM-peri FinFET – A Thermally-stable High-Performance Advanced CMOS RMG Platform with Mo-based pWFM for sub-10nm DRAM
- Thursday, June 20 • 3:25 PM - 3:50 PM
- T16.1 | Unveiling the Impact of AC PBTI on Hydrogen Formation in Oxide Semiconductor Transistors
- Thursday, June 20 • 3:25 PM - 3:50 PM
- C28 | Processors II
- Thursday, June 20 • 3:25 PM - 5:05 PM
- C29 | PLLs
- Thursday, June 20 • 3:25 PM - 5:05 PM
- T15 | Non-Volatile Memory Technology - Hafnia Based Ferroelectrics-2
- Thursday, June 20 • 3:25 PM - 5:30 PM
- T16 | Reliability, Characterization & Modeling of Oxide Semiconductor and Si Devices-2
- Thursday, June 20 • 3:25 PM - 5:30 PM
- T17 | Memory Technology: NAND, DRAM-2
- Thursday, June 20 • 3:25 PM - 5:30 PM
- T17.2 | 4F2 Stackable Polysilicon Channel Access Device for Ultra-Dense NVDRAM
- Thursday, June 20 • 3:50 PM - 4:15 PM
- T15.2 | Revealing Mechanism of Non-accumulative Disturb and Approach Toward Disturb Suppression in HZO/Si FeFET Memory
- Thursday, June 20 • 3:50 PM - 4:15 PM
- T16.2 | Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of Oxide Semiconductor Transistors
- Thursday, June 20 • 3:50 PM - 4:15 PM
- C29.2 | A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur
- Thursday, June 20 • 3:50 PM - 4:15 PM
- C28.2 | A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup
- Thursday, June 20 • 3:50 PM - 4:15 PM
- C28.3 | A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices
- Thursday, June 20 • 4:15 PM - 4:40 PM
- C29.3 | A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
- Thursday, June 20 • 4:15 PM - 4:40 PM
- T16.3 | Positive to Negative Schottky Barrier Transition in Metal/Oxide Semiconductor Contacts by Tuning Indium Concentration in IGZO
- Thursday, June 20 • 4:15 PM - 4:40 PM
- T15.3 | BEOL Compatible Ultra-Low Operating Voltage (0.5 V) and Preconfigured Switching Polarization States in Effective 3 nm Ferroelectric HZO Capacitors
- Thursday, June 20 • 4:15 PM - 4:40 PM
- T17.3 | A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades (Late News)
- Thursday, June 20 • 4:15 PM - 4:40 PM
- T17.4 | Cell to Core-Periphery Overlap (C2O) based on BCAT for next generation DRAM
- Thursday, June 20 • 4:40 PM - 5:05 PM
- T16.4 | Fluorine Plasma Treatment-Enabled ITO Transistor Excellent Reliability and Comprehensive Understanding of Temperature Dependence from 77 K to 375 K
- Thursday, June 20 • 4:40 PM - 5:05 PM
- C29.4 | A 5GHz Fractional-N PLL with 97fsrms Jitter and -255.3dB FoM
- Thursday, June 20 • 4:40 PM - 5:05 PM
- C28.4 | An 11.4mm2 40.2Gbps 17.4pJ/b/iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communication
- Thursday, June 20 • 4:40 PM - 5:05 PM
- T15.4 | Comprehensive Analysis of Duty-cycle Induced Degradations in HfxZr1-xO2-based Ferroelectric Capacitor Behavior, Modeling, and Optimization
- Thursday, June 20 • 4:40 PM - 5:05 PM
- T16.5 | A Novel Method for Extracting Asymmetric Source and Drain Resistance in IGZO Vertical Channel Transistors
- Thursday, June 20 • 5:05 PM - 5:30 PM
- T15.5 | Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 µC/cm2 with Endurance > 4E12
- Thursday, June 20 • 5:05 PM - 5:30 PM
- T17.5 | Single metal BCAT breakthrough to open a new era of 12 nm DRAM and beyond
- Thursday, June 20 • 5:05 PM - 5:30 PM